Active pixel sensor arrays, such as may be employed to advantage in CMOS imaging arrays, are well known in the art. In such arrays, active pixels, usually arrayed in columns and rows, generate an output voltage having a magnitude related to the intensity of light of an image impending on the pixels. The output magnitudes are then quantized to permit digital storage and/or display of the image.
Sampling circuits are generally utilized for reading the pixel voltage of each pixel. To that end, the pixel voltage of each pixel is sampled and held by a corresponding respective column sample and hold circuit. The pixel voltage of all pixels in a row of pixels are sampled in parallel.
Following sampling of the row of pixels, a reset voltage associated with each pixel is also sampled. Hence, associated with each pixel voltage sample and hold circuit is a reset voltage sample and hold circuit. The need for such reset voltages is well known in the art. The reset voltages for all pixels in a row of pixels are also sampled and held in parallel following the pixel voltage sampling.
With each pixel and reset voltage sampled and held for each pixel in a row of pixels, the pixel voltage and reset voltages for each pixel are then read together for storage or display. The pixel and reset voltage for each pixel when read may be inputted to a differential amplifier which subtracts the pixel voltage from the reset voltage to provide a differential voltage which is then quantized for storage and display. The pixel and reset voltages of the pixels are read in series, one pixel at a time, until all of the pixel and reset voltages of a row of pixels are read. Then, the next row of pixels are addressed and the above process is repeated.
The need for accurate and reliable pixel voltage and reset voltage reading is critical to a quality image reproduction. Any sampling errors, especially those of a repetitive nature, can result in, for example, column wise noise and unwanted horizontal stripes in the final image. Such image imperfections may be readily perceptible by the human eye.
Prior sampling circuits have utilized differential source-follower-type buffers for sampling and holding pixel and reset voltages. These circuits suffer from sources of error such as source-follower transistor mismatch, current source mismatch, sampling error mismatch, and signal dependent charge injection. All of these errors can be coherent in nature and result in perceptible column-wise error. The present invention is therefore generally directed to a sample and hold circuit which may be employed to advantage in active pixel sampling array systems which avoid the coherent errors mentioned above. Active pixel sensor arrays, such as may be employed to advantage in CMOS imaging arrays, are well known in the art. In such arrays, active pixels, usually arrayed in columns and rows, generate an output voltage having a magnitude related to the intensity of light of an image impending on the pixels. The output magnitudes are then quantized to permit digital storage and/or display of the image.
Sampling circuits are generally utilized for reading the pixel voltage of each pixel. To that end, the pixel voltage of each pixel is sampled and held by a corresponding respective column sample and hold circuit. The pixel voltage of all pixels in a row of pixels are sampled in parallel.
Following sampling of the row of pixels, a reset voltage associated with each pixel is also sampled. Hence, associated with each pixel voltage sample and hold circuit is a reset voltage sample and hold circuit. The need for such reset voltages is well known in the art. The reset voltages for all pixels in a row of pixels are also sampled and held in parallel following the pixel voltage sampling.
With each pixel and reset voltage sampled and held for each pixel in a row of pixels, the pixel voltage and reset voltages for each pixel are then read together for storage or display. The pixel and reset voltage for each pixel when read may be inputted to a differential amplifier which subtracts the pixel voltage from the reset voltage to provide a differential voltage which is then quantized for storage and display. The pixel and reset voltages of the pixels are read in series, one pixel at a time, until all of the pixel and reset voltages of a row of pixels are read. Then, the next row of pixels are addressed and the above process is repeated.
The need for accurate and reliable pixel voltage and reset voltage reading is critical to a quality image reproduction. Any sampling errors, especially those of a repetitive nature, can result in, for example, column wise noise and unwanted horizontal stripes in the final image. Such image imperfections may be readily perceptible by the human eye.
Prior sampling circuits have utilized differential source-follower-type buffers for sampling and holding pixel and reset voltages. These circuits suffer from sources of error such as source-follower transistor mismatch, current source mismatch, sampling error mismatch, and signal dependent charge injection. All of these errors can be coherent in nature and result in perceptible column-wise error. The present invention is therefore generally directed to a sample and hold circuit which may be employed to advantage in active pixel sampling array systems which avoid the coherent errors mentioned above.